1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a vertical channel transistor array and a manufacturing method thereof.
2. Description of Related Art
With the development of powerful microprocessors, software is more capable of programming and calculating an increasing amount of data. Therefore, the fabrication of memories has become essential in the semiconductor industry. A dynamic random access memory (DRAM) is a volatile memory (VM) and is constituted by a plurality of memory cells. Each of the memory cells in the VM is mainly composed of a transistor and a capacitor, and all memory cells are electrically connected to one another through word lines (WL) and bit lines (BL).
As science advances day by day, the length of the channel region of each transistor in the DRAM is gradually decreased together with the reduction of the device dimension, so as to accelerate the operation of the device. Thereby, however, a significant short channel effect occurs in the transistors, and an On current is likely to decrease.
Accordingly, a conventional solution aims to change the horizontal transistor into the vertical transistor. In such a DRAM structure, the vertical transistors are formed in trenches, and embedded bit lines and embedded word lines are formed, as disclosed in U.S. Pat. No. 7,355,230.
Owing to increasing integrity of semiconductor devices, the dimension of the semiconductor devices needs to be decreased. As such, complexity of the semiconductor manufacturing process is raised, and electrical performance of the semiconductor is likely to be affected. Currently, researches are directed to formation of semiconductor devices with the reduced size and favorable performance.